Enum iced_x86::CpuidFeature

source · [−]

#[non_exhaustive]
pub enum CpuidFeature {
Show 162 variants    INTEL8086,
    INTEL8086_ONLY,
    INTEL186,
    INTEL286,
    INTEL286_ONLY,
    INTEL386,
    INTEL386_ONLY,
    INTEL386_A0_ONLY,
    INTEL486,
    INTEL486_A_ONLY,
    UMOV,
    IA64,
    X64,
    ADX,
    AES,
    AVX,
    AVX2,
    AVX512_4FMAPS,
    AVX512_4VNNIW,
    AVX512_BF16,
    AVX512_BITALG,
    AVX512_IFMA,
    AVX512_VBMI,
    AVX512_VBMI2,
    AVX512_VNNI,
    AVX512_VP2INTERSECT,
    AVX512_VPOPCNTDQ,
    AVX512BW,
    AVX512CD,
    AVX512DQ,
    AVX512ER,
    AVX512F,
    AVX512PF,
    AVX512VL,
    BMI1,
    BMI2,
    CET_IBT,
    CET_SS,
    CL1INVMB,
    CLDEMOTE,
    CLFLUSHOPT,
    CLFSH,
    CLWB,
    CLZERO,
    CMOV,
    CMPXCHG16B,
    CPUID,
    CX8,
    D3NOW,
    D3NOWEXT,
    OSS,
    ENQCMD,
    F16C,
    FMA,
    FMA4,
    FPU,
    FPU287,
    FPU287XL_ONLY,
    FPU387,
    FPU387SL_ONLY,
    FSGSBASE,
    FXSR,
    CYRIX_D3NOW,
    GFNI,
    HLE,
    HLE_or_RTM,
    INVEPT,
    INVPCID,
    INVVPID,
    LWP,
    LZCNT,
    MCOMMIT,
    MMX,
    MONITOR,
    MONITORX,
    MOVBE,
    MOVDIR64B,
    MOVDIRI,
    MPX,
    MSR,
    MULTIBYTENOP,
    PADLOCK_ACE,
    PADLOCK_PHE,
    PADLOCK_PMM,
    PADLOCK_RNG,
    PAUSE,
    PCLMULQDQ,
    PCOMMIT,
    PCONFIG,
    PKU,
    POPCNT,
    PREFETCHW,
    PREFETCHWT1,
    PTWRITE,
    RDPID,
    RDPMC,
    RDPRU,
    RDRAND,
    RDSEED,
    RDTSCP,
    RTM,
    SEP,
    SGX1,
    SHA,
    SKINIT,
    SKINIT_or_SVM,
    SMAP,
    SMX,
    SSE,
    SSE2,
    SSE3,
    SSE4_1,
    SSE4_2,
    SSE4A,
    SSSE3,
    SVM,
    SEV_ES,
    SYSCALL,
    TBM,
    TSC,
    VAES,
    VMX,
    VPCLMULQDQ,
    WAITPKG,
    WBNOINVD,
    XOP,
    XSAVE,
    XSAVEC,
    XSAVEOPT,
    XSAVES,
    SEV_SNP,
    SERIALIZE,
    TSXLDTRK,
    INVLPGB,
    AMX_BF16,
    AMX_TILE,
    AMX_INT8,
    CYRIX_FPU,
    CYRIX_SMM,
    CYRIX_SMINT,
    CYRIX_SMINT_0F7E,
    CYRIX_SHR,
    CYRIX_DDI,
    CYRIX_EMMI,
    CYRIX_DMI,
    CENTAUR_AIS,
    MOV_TR,
    SMM,
    TDX,
    KL,
    AESKLE,
    WIDE_KL,
    UINTR,
    HRESET,
    AVX_VNNI,
    PADLOCK_GMI,
    FRED,
    LKGS,
    AVX512_FP16,
    UDBG,
    KNC,
    PADLOCK_UNDOC,
}

Expand description

CPUID feature flags

Variants (Non-exhaustive)

This enum is marked as non-exhaustive

Non-exhaustive enums could have additional variants added in future. Therefore, when matching against variants of non-exhaustive enums, an extra wildcard arm must be added to account for any future variants.

`INTEL8086`

8086 or later

`INTEL8086_ONLY`

8086 only

`INTEL186`

80186 or later

`INTEL286`

80286 or later

`INTEL286_ONLY`

80286 only

`INTEL386`

80386 or later

`INTEL386_ONLY`

80386 only

`INTEL386_A0_ONLY`

80386 A0-B0 stepping only (XBTS, IBTS instructions)

`INTEL486`

Intel486 or later

`INTEL486_A_ONLY`

Intel486 A stepping only (CMPXCHG)

`UMOV`

UMOV (80386 and Intel486)

`IA64`

IA-64

`X64`

CPUID.80000001H:EDX.LM[bit 29]

`ADX`

CPUID.(EAX=07H, ECX=0H):EBX.ADX[bit 19]

`AES`

CPUID.01H:ECX.AES[bit 25]

`AVX`

CPUID.01H:ECX.AVX[bit 28]

`AVX2`

CPUID.(EAX=07H, ECX=0H):EBX.AVX2[bit 5]

`AVX512_4FMAPS`

CPUID.(EAX=07H, ECX=0H):EDX.AVX512_4FMAPS[bit 3]

`AVX512_4VNNIW`

CPUID.(EAX=07H, ECX=0H):EDX.AVX512_4VNNIW[bit 2]

`AVX512_BF16`

CPUID.(EAX=07H, ECX=1H):EAX.AVX512_BF16[bit 5]

`AVX512_BITALG`

CPUID.(EAX=07H, ECX=0H):ECX.AVX512_BITALG[bit 12]

`AVX512_IFMA`

CPUID.(EAX=07H, ECX=0H):EBX.AVX512_IFMA[bit 21]

`AVX512_VBMI`

CPUID.(EAX=07H, ECX=0H):ECX.AVX512_VBMI[bit 1]

`AVX512_VBMI2`

CPUID.(EAX=07H, ECX=0H):ECX.AVX512_VBMI2[bit 6]

`AVX512_VNNI`

CPUID.(EAX=07H, ECX=0H):ECX.AVX512_VNNI[bit 11]

`AVX512_VP2INTERSECT`

CPUID.(EAX=07H, ECX=0H):EDX.AVX512_VP2INTERSECT[bit 08]

`AVX512_VPOPCNTDQ`

CPUID.(EAX=07H, ECX=0H):ECX.AVX512_VPOPCNTDQ[bit 14]

`AVX512BW`

CPUID.(EAX=07H, ECX=0H):EBX.AVX512BW[bit 30]

`AVX512CD`

CPUID.(EAX=07H, ECX=0H):EBX.AVX512CD[bit 28]

`AVX512DQ`

CPUID.(EAX=07H, ECX=0H):EBX.AVX512DQ[bit 17]

`AVX512ER`

CPUID.(EAX=07H, ECX=0H):EBX.AVX512ER[bit 27]

`AVX512F`

CPUID.(EAX=07H, ECX=0H):EBX.AVX512F[bit 16]

`AVX512PF`

CPUID.(EAX=07H, ECX=0H):EBX.AVX512PF[bit 26]

`AVX512VL`

CPUID.(EAX=07H, ECX=0H):EBX.AVX512VL[bit 31]

`BMI1`

CPUID.(EAX=07H, ECX=0H):EBX.BMI1[bit 3]

`BMI2`

CPUID.(EAX=07H, ECX=0H):EBX.BMI2[bit 8]

`CET_IBT`

CPUID.(EAX=07H, ECX=0H):EDX.CET_IBT[bit 20]

`CET_SS`

CPUID.(EAX=07H, ECX=0H):ECX.CET_SS[bit 7]

`CL1INVMB`

CL1INVMB instruction (Intel SCC = Single-Chip Computer)

`CLDEMOTE`

CPUID.(EAX=07H, ECX=0H):ECX.CLDEMOTE[bit 25]

`CLFLUSHOPT`

CPUID.(EAX=07H, ECX=0H):EBX.CLFLUSHOPT[bit 23]

`CLFSH`

CPUID.01H:EDX.CLFSH[bit 19]

`CLWB`

CPUID.(EAX=07H, ECX=0H):EBX.CLWB[bit 24]

`CLZERO`

CPUID.80000008H:EBX.CLZERO[bit 0]

`CMOV`

CPUID.01H:EDX.CMOV[bit 15]

`CMPXCHG16B`

CPUID.01H:ECX.CMPXCHG16B[bit 13]

`CPUID`

RFLAGS.ID can be toggled

`CX8`

CPUID.01H:EDX.CX8[bit 8]

`D3NOW`

CPUID.80000001H:EDX.3DNOW[bit 31]

`D3NOWEXT`

CPUID.80000001H:EDX.3DNOWEXT[bit 30]

`OSS`

CPUID.(EAX=12H, ECX=0H):EAX.OSS[bit 5]

`ENQCMD`

CPUID.(EAX=07H, ECX=0H):ECX.ENQCMD[bit 29]

`F16C`

CPUID.01H:ECX.F16C[bit 29]

`FMA`

CPUID.01H:ECX.FMA[bit 12]

`FMA4`

CPUID.80000001H:ECX.FMA4[bit 16]

`FPU`

8087 or later (CPUID.01H:EDX.FPU[bit 0])

`FPU287`

80287 or later

`FPU287XL_ONLY`

80287XL only

`FPU387`

80387 or later

`FPU387SL_ONLY`

80387SL only

`FSGSBASE`

CPUID.(EAX=07H, ECX=0H):EBX.FSGSBASE[bit 0]

`FXSR`

CPUID.01H:EDX.FXSR[bit 24]

`CYRIX_D3NOW`

Cyrix (AMD Geode GX/LX) 3DNow! instructions

`GFNI`

CPUID.(EAX=07H, ECX=0H):ECX.GFNI[bit 8]

`HLE`

CPUID.(EAX=07H, ECX=0H):EBX.HLE[bit 4]

`HLE_or_RTM`

HLE or RTM

`INVEPT`

IA32_VMX_EPT_VPID_CAP[bit 20]

`INVPCID`

CPUID.(EAX=07H, ECX=0H):EBX.INVPCID[bit 10]

`INVVPID`

IA32_VMX_EPT_VPID_CAP[bit 32]

`LWP`

CPUID.80000001H:ECX.LWP[bit 15]

`LZCNT`

CPUID.80000001H:ECX.LZCNT[bit 5]

`MCOMMIT`

CPUID.80000008H:EBX.MCOMMIT[bit 8]

`MMX`

CPUID.01H:EDX.MMX[bit 23]

`MONITOR`

CPUID.01H:ECX.MONITOR[bit 3]

`MONITORX`

CPUID.80000001H:ECX.MONITORX[bit 29]

`MOVBE`

CPUID.01H:ECX.MOVBE[bit 22]

`MOVDIR64B`

CPUID.(EAX=07H, ECX=0H):ECX.MOVDIR64B[bit 28]

`MOVDIRI`

CPUID.(EAX=07H, ECX=0H):ECX.MOVDIRI[bit 27]

`MPX`

CPUID.(EAX=07H, ECX=0H):EBX.MPX[bit 14]

`MSR`

CPUID.01H:EDX.MSR[bit 5]

`MULTIBYTENOP`

Multi-byte nops (0F1F /0): CPUID.01H.EAX[Bits 11:8] = 0110B or 1111B

`PADLOCK_ACE`

CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.ACE[Bits 7:6] = 11B ([6] = exists, [7] = enabled)

`PADLOCK_PHE`

CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.PHE[Bits 11:10] = 11B ([10] = exists, [11] = enabled)

`PADLOCK_PMM`

CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.PMM[Bits 13:12] = 11B ([12] = exists, [13] = enabled)

`PADLOCK_RNG`

CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.RNG[Bits 3:2] = 11B ([2] = exists, [3] = enabled)

`PAUSE`

PAUSE instruction (Pentium 4 or later)

`PCLMULQDQ`

CPUID.01H:ECX.PCLMULQDQ[bit 1]

`PCOMMIT`

CPUID.(EAX=07H, ECX=0H):EBX.PCOMMIT[bit 22]

`PCONFIG`

CPUID.(EAX=07H, ECX=0H):EDX.PCONFIG[bit 18]

`PKU`

CPUID.(EAX=07H, ECX=0H):ECX.PKU[bit 3]

`POPCNT`

CPUID.01H:ECX.POPCNT[bit 23]

`PREFETCHW`

CPUID.80000001H:ECX.PREFETCHW[bit 8]

`PREFETCHWT1`

CPUID.(EAX=07H, ECX=0H):ECX.PREFETCHWT1[bit 0]

`PTWRITE`

CPUID.(EAX=14H, ECX=0H):EBX.PTWRITE[bit 4]

`RDPID`

CPUID.(EAX=07H, ECX=0H):ECX.RDPID[bit 22]

`RDPMC`

RDPMC instruction (Pentium MMX or later, or Pentium Pro or later)

`RDPRU`

CPUID.80000008H:EBX.RDPRU[bit 4]

`RDRAND`

CPUID.01H:ECX.RDRAND[bit 30]

`RDSEED`

CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18]

`RDTSCP`

CPUID.80000001H:EDX.RDTSCP[bit 27]

`RTM`

CPUID.(EAX=07H, ECX=0H):EBX.RTM[bit 11]

`SEP`

CPUID.01H:EDX.SEP[bit 11]

`SGX1`

CPUID.(EAX=12H, ECX=0H):EAX.SGX1[bit 0]

`SHA`

CPUID.(EAX=07H, ECX=0H):EBX.SHA[bit 29]

`SKINIT`

CPUID.80000001H:ECX.SKINIT[bit 12]

`SKINIT_or_SVM`

SKINIT or SVM

`SMAP`

CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20]

`SMX`

CPUID.01H:ECX.SMX[bit 6]

`SSE`

CPUID.01H:EDX.SSE[bit 25]

`SSE2`

CPUID.01H:EDX.SSE2[bit 26]

`SSE3`

CPUID.01H:ECX.SSE3[bit 0]

`SSE4_1`

CPUID.01H:ECX.SSE4_1[bit 19]

`SSE4_2`

CPUID.01H:ECX.SSE4_2[bit 20]

`SSE4A`

CPUID.80000001H:ECX.SSE4A[bit 6]

`SSSE3`

CPUID.01H:ECX.SSSE3[bit 9]

`SVM`

CPUID.80000001H:ECX.SVM[bit 2]

`SEV_ES`

CPUID.8000001FH:EAX.SEV-ES[bit 3]

`SYSCALL`

CPUID.80000001H:EDX.SYSCALL[bit 11]

`TBM`

CPUID.80000001H:ECX.TBM[bit 21]

`TSC`

CPUID.01H:EDX.TSC[bit 4]

`VAES`

CPUID.(EAX=07H, ECX=0H):ECX.VAES[bit 9]

`VMX`

CPUID.01H:ECX.VMX[bit 5]

`VPCLMULQDQ`

CPUID.(EAX=07H, ECX=0H):ECX.VPCLMULQDQ[bit 10]

`WAITPKG`

CPUID.(EAX=07H, ECX=0H):ECX.WAITPKG[bit 5]

`WBNOINVD`

CPUID.(EAX=80000008H, ECX=0H):EBX.WBNOINVD[bit 9]

`XOP`

CPUID.80000001H:ECX.XOP[bit 11]

`XSAVE`

CPUID.01H:ECX.XSAVE[bit 26]

`XSAVEC`

CPUID.(EAX=0DH, ECX=1H):EAX.XSAVEC[bit 1]

`XSAVEOPT`

CPUID.(EAX=0DH, ECX=1H):EAX.XSAVEOPT[bit 0]

`XSAVES`

CPUID.(EAX=0DH, ECX=1H):EAX.XSAVES[bit 3]

`SEV_SNP`

CPUID.8000001FH:EAX.SEV-SNP[bit 4]

`SERIALIZE`

CPUID.(EAX=07H, ECX=0H):EDX.SERIALIZE[bit 14]

`TSXLDTRK`

CPUID.(EAX=07H, ECX=0H):EDX.TSXLDTRK[bit 16]

`INVLPGB`

CPUID.80000008H:EBX.INVLPGB[bit 3]

`AMX_BF16`

CPUID.(EAX=07H, ECX=0H):EDX.AMX-BF16[bit 22]

`AMX_TILE`

CPUID.(EAX=07H, ECX=0H):EDX.AMX-TILE[bit 24]

`AMX_INT8`

CPUID.(EAX=07H, ECX=0H):EDX.AMX-INT8[bit 25]

`CYRIX_FPU`

Cyrix FPU instructions (Cyrix, AMD Geode GX/LX)

`CYRIX_SMM`

Cyrix SMM instructions: SVDC, RSDC, SVLDT, RSLDT, SVTS, RSTS (Cyrix, AMD Geode GX/LX)

`CYRIX_SMINT`

Cyrix SMINT 0F38 (6x86MX and later, AMD Geode GX/LX)

`CYRIX_SMINT_0F7E`

Cyrix SMINT 0F7E (6x86 or earlier)

`CYRIX_SHR`

Cyrix SMM instructions: RDSHR, WRSHR (6x86MX, M II, Cyrix III)

`CYRIX_DDI`

Cyrix DDI instructions: BB0_Reset, BB1_Reset, CPU_READ, CPU_WRITE (MediaGX, GXm, GXLV, GX1)

`CYRIX_EMMI`

Cyrix AND CPUID.80000001H:EDX.EMMI[bit 24]

`CYRIX_DMI`

Cyrix DMI instructions: DMINT, RDM (AMD Geode GX/LX)

`CENTAUR_AIS`

CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.AIS[Bits 1:0] = 11B ([0] = exists, [1] = enabled)

`MOV_TR`

MOV to/from TR (80386, Intel486, Cyrix, Geode)

`SMM`

RSM instruction (some 386s, some 486s, Pentium and later)

`TDX`

CPUID.(EAX=??H, ECX=?H):???.????[bit ??]

`KL`

CPUID.(EAX=07H, ECX=0H):ECX.KL[bit 23]

`AESKLE`

CPUID.19H:EBX.AESKLE[bit 0]

`WIDE_KL`

CPUID.19H:EBX.WIDE_KL[bit 2]

`UINTR`

CPUID.(EAX=07H, ECX=0H):EDX.UINTR[bit 5]

`HRESET`

CPUID.(EAX=07H, ECX=01H):EAX.HRESET[bit 22]

`AVX_VNNI`

CPUID.(EAX=07H, ECX=01H):EAX.AVX-VNNI[bit 4]

`PADLOCK_GMI`

CPUID.0C0000000H:EAX >= 0C0000001H AND CPUID.0C0000001H:EDX.GMI[Bits 5:4] = 11B ([4] = exists, [5] = enabled)

`FRED`

CPUID.(EAX=07H, ECX=01H):EAX.FRED[bit 17]

`LKGS`

CPUID.(EAX=07H, ECX=01H):EAX.LKGS[bit 18]

`AVX512_FP16`

CPUID.(EAX=07H, ECX=0H):EDX.AVX512-FP16[bit 23]

`UDBG`

Undocumented Intel RDUDBG and WRUDBG instructions

`KNC`

Intel Knights Corner

`PADLOCK_UNDOC`

Undocumented instruction

Implementations

source

impl CpuidFeature

source

pub fn values(
) -> impl Iterator<Item = CpuidFeature> + DoubleEndedIterator + ExactSizeIterator + FusedIterator

Iterates over all CpuidFeature enum values

Trait Implementations

source

impl Clone for CpuidFeature

source

fn clone(&self) -> CpuidFeature

Returns a copy of the value. Read more

Feeds a slice of this type into the given Hasher. Read more

source

impl Ord for CpuidFeature

source

fn cmp(&self, other: &CpuidFeature) -> Ordering

This method returns an Ordering between self and other. Read more

1.21.0 · source

const fn max(self, other: Self) -> Self

Compares and returns the maximum of two values. Read more

1.21.0 · source

const fn min(self, other: Self) -> Self

Compares and returns the minimum of two values. Read more

1.50.0 · source

const fn clamp(self, min: Self, max: Self) -> Selfwhere
Self: PartialOrd<Self>,

Restrict a value to a certain interval. Read more

source

impl PartialEq<CpuidFeature> for CpuidFeature

source

fn eq(&self, other: &CpuidFeature) -> bool

This method tests for self and other values to be equal, and is used by ==. Read more

1.0.0 · source

const fn ne(&self, other: &Rhs) -> bool

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason. Read more

source

impl Send for CpuidFeature

impl Sync for CpuidFeature

impl Unpin for CpuidFeature

fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

source

impl<T> ToOwned for Twhere
T: Clone,

type Owned = T